Nanotechnology has gained widespread use in the semiconductor industry as a way to meet scaled technology requirements. For example, nanowires are currently being used to form the channel regions in field-effect transistors (FETs).
Integrating nanowires in FET devices, however, presents several notable challenges. First, trying to in-situ dope nanowires during their growth is difficult since dopants are incorporated into the nanowire from the gas-phase and/or by radial growth. See, for example, E. Tutuc, et al., “Realization of a Linear Germanium Nanowire p-n Junction,” Nano Lett. 6(9):2070-4 (Sep. 2006). For example, counter-doping of a lightly doped portion of a nanowire can occur if a following heavily doped segment is grown. Second, the onset for a doped region in an in-situ doped nanowire, due to growth incubation time, will exhibit variations corresponding to the delay in nucleation experienced for each nanowire. See, for example, B. Kalache et al., “Observation of Incubation Times in the Nucleation of Silicon Nanowires Obtained by the Vapor-Liquid-Solid Method,” Jpn. J. Appl. Phys. Vol. 45, No. 7, pp. L190-L193(2006). Third, heavy in-situ doping can lead to nanowire tapering, i.e., in germanium (Ge) nanowires, and loss of gold (Au) from the catalyst, i.e., in silicon (Si) nanowires doped with diborane. Fourth, even if segmented doping along a nanowire body can be achieved, there are no simple methods to align the contacts and the gate to each segment. Fifth, dopant variations make it hard to control doping in thin nanowires.
To build a nanowire FET, the nanowire should have an n-p-n (n-FET) or a p-n-p (p-FET) doping profile along its main axis. Several techniques have been proposed to achieve such a doping profile. The first technique involves in-situ doping of the nanowire during growth. See, for example, Y. Wang et al., “Inversion-Mode Operation of Thermally-Oxidized Modulation-Doped Silicon Nanowire Field Effect Transistor,” Device Research Conference Digest, p. 175 (2006). The disadvantages of the in-situ doping technique were described above. The second approach is based on ion implantation. See, for example, O. Hayden et al., “Fully Depleted Nanowire Field-Effect Transistor in Inversion Mode,” Small 3, p. 230 (2007). An ion implantation approach is disadvantageous in that it can only be used with thick nanowires (i.e., nanowires having diameters of greater than about 30 nanometers (nm)) since smaller nanowires will be amorphized and sputtered by the implant. Recrystallization of the doped regions may not be possible, due to the one-dimensional nature of the nanowire (because spontaneous recrystallization will dominate during solid phase epitaxy).
More recently, epitaxial doped contacts to nanowires were realized by epitaxially thickening the nanowire body in the source and drain regions of a FET device, i.e., analogous to the raised source/drain method used for thin silicon-on-insulator (SOI) FETs. See, for example, G. M. Cohen et al., “Nanowire Metal-Oxide-Semiconductor Field Effect Transistor with Doped Epitaxial Contacts for Source and Drain,” Appl. Phys. Lett. 90, 233110 (2007). In this approach, non-selective ultra-high vacuum chemical vapor deposition (UHV—CVD) of silicon is used for epitaxy that templates from the body of a single crystal nanowire. Non-selective Si deposition, however, has several drawbacks. First, Si is deposited everywhere. As such, any excess Si that bridges the source and drain regions has to be removed to achieve electrical isolation. Second, only the Si that templates from the nanowire is a single crystal. Thus, at some distance from the nanowire the deposited Si will be poly-crystalline, i.e., poly-silicon (poly-Si). Poly-Si typically exhibits higher resistivity than single-crystal Si, thus increasing the overall contact resistance of the device.
Thus, there exists a need for improved nanowire FET devices and techniques for the fabrication thereof.